1. Technical Field of the Invention
The present invention relates to power supplies for integrated circuit memories and, more particularly, to a memory receiving switchable power supply sets of voltages depending on active and standby mode operation.
2. Description of Related Art
Reference is made to FIG. 1 which is a schematic diagram of a standard six transistor static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are controlled by a word line (WL). Transistor 20 is connected between the true node 16 and a true bit line (BLT). Transistor 22 is connected between the complement node 18 and a complement bit line (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high voltage at a high voltage VH node, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low voltage at a low voltage VL node. The high voltage VH and the low voltage VL comprise a power supply set of voltages for the cell 10. Conventionally, the high voltage VH is a positive voltage (for example, 1.5V) and the low voltage VL is a ground voltage (for example, 0V). In an integrated circuit including the SRAM cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage converter circuit which receives some other set of voltages received from the pins of the chip. The power supply set of voltages VH and VL are conventionally applied to the SRAM cell 10 at all times that the cell/integrated circuit is operational.
Reference is now made to FIG. 2 which is a block diagram of a static random access memory (SRAM) array 30. The array 30 includes a plurality of SRAM cells 10 arranged in an matrix format. The number of cells 10 included in the array 30 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL of the power supply set of voltages is applied to the array 30 and distributed over the array in a manner well known to those skilled in the art to the individual ones of the included cells 10 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1).
Reference is now made to FIG. 3 which is a block diagram of a static random access memory (SRAM) array 40. The array 40 is comprised of a plurality of memory blocks 42 arranged in a matrix format. The number of blocks 42 included in the array 40 can widely vary depending on the circuit designer's needs. Each block 42 includes a plurality of SRAM cells 10 also arranged in a matrix format. The number of cells 10 included in the block 42 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL of the power supply set of voltages is applied to the array 40 and distributed over the array by a power distribution grid in a manner well known to those skilled in the art to each of the blocks 42. Power is then passed on to the individual ones of the included cells 10 within each block 42 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1).
As the integrated circuit (IC) industry shifts from high performance and often high power consumption devices to more energy efficient devices using state of the art fabrication processes, new low power design techniques are required. Specifically, in some battery powered devices maximizing speed is a secondary consideration to minimizing power consumption.
To retain data in a static random access memory (SRAM), power must be applied to the cell. If power is removed from the cell then the data stored therein is lost. It is likely that for a majority of the time that power is being applied to the memory cell, that power is being consumed in a standby or wait mode between instances of a read or write operation (active read/write mode). There is a need in the art to consider ways to reduce the power consumed while an SRAM cell is in standby waiting to be written or read. This is especially of concern when the memory is powered from a battery power source, and when the array becomes very large in size.
Wafer fabrication processes are developed to produce integrated circuits that have the best balance of electronic properties. The goal is to have high performance at the lowest possible power consumption. Some applications require the balance to be shifted more toward higher performance, while other applications require shifting balance toward lower power consumption. Other parameters known in the art are considered by the circuit designer to determine the characteristics of an integrated circuit.
The transistors used in the memory device are engineered by wafer fabrication process engineers to provide the best performance at the lowest power consumption. Newer state of the art processes seek to improve these characteristics over previous processes. The circuit designer also uses techniques to optimize this performance.
A given integrated circuit process typically has an optimal supply set of voltages (high voltage and low voltage) that powers the transistors. This voltage set parameter gives the best performance under most circumstances, but not necessarily in all circumstances. For an SRAM, this voltage set may be fine for the period of time during which the memory is being written or read. When the memory is at rest waiting for the next access (standby mode), however, this voltage may not be optimum.
For applications that run on a battery, power consumption is the most critical specification. For circuits used in these applications design efforts are primarily focused on using circuits that consume the minimal amount of power.
It is known in the art that integrated circuit transistors have non-ideal characteristics that draw power even when not active. These “leakage” currents can add up to be a serious problem in a circuit, such as a memory array, which includes a large number of transistors. Generally, the higher the high voltage of the voltage set, the higher the potential leakage current which can occur. A need accordingly exists to address this leakage current problem and preferably reduce leakage current across a memory array.